There is a higher integration requirement in the field of semiconductor packages. A semiconductor chip is usually mounted on a substrate (such as a ceramic package) and is electrically connected to the substrate through the wires within the substrate. The substrate having the semiconductor chip mounted thereon is mounted on a larger substrate called a multilayer printed-circuit board and is electrically connected to the printed-circuit board through the wires within the printed-circuit board. With this structure, the space between electrodes of the semiconductor chip is expanded from 0.1 millimeters (mm)--0.25 mm to 0.3 mm--0.5 mm.
In order to obtain a function such as a semiconductor package has when a semiconductor chip is packaged with a multilayer single-sided or two-sided printed circuit board, the signal lines, power supply lines, and ground lines are pulled from the foot print (electrode) of the chip toward the outer circumference of the printed circuit board. These lines are wiring-connected using through holes (a hole completely passing through the printed circuit board) bored in the printed circuit board to a predetermined position adjacent a mother board. These through holes are usually arranged in the outer circumference of the multilayer printed circuit board. This is because, if the through holes are arranged near the chip, i.e., in the central position of the multilayer printed circuit board, they will hinder the lines being pulling out of the chip.
The wirings formed in the multilayer printed circuit board are connected by holes (via-holes) formed in a plurality of wirings layers provided on a substrate that is part of the printed circuit board. A method of building up wiring layers including such via-holes one layer by one layer is called a building-up method. A multilayer structure formed by the building-up method is referred to as a surface laminar circuit (SLC) structure/layer. A section of the SLC structure is shown in FIG. 1. This structure is formed, for example, by coating a photosensitive insulation layer 2 on a substrate 1 of a printed circuit board 6, forming a via-hole 3 in the insulation layer 2, and forming on the via-hole 3 a wiring layer 4 having a predetermined pattern by photoetching. This via-hole 3 is a small hole for electrically connecting the wiring layers built up one layer by one layer. A number of layers thus formed are built up to form a SLC layer. This wiring layer 4, together with the via-hole 3, electrically connects a large number of connection terminals (not shown) extending from a semiconductor chip to be mounted on the substrate 1, and exhibits a predetermined function. In the SLC structure, the electrical connection between layers is established by the via-hole 3 instead of a through hole 5. As a result, the degree of freedom of the wiring is increased.
The printed circuit board is mounted on the mother board. The printed circuit board and the mother board are interconnected by the wiring provided on the boards and exhibit a predetermined function. In order to connect a connection terminal of the chip and a solder bump (a connection terminal to the printed circuit board), a conductive channel passing through the substrate of the printed circuit board is needed. This is because the connection terminal of the chip and the solder bump are provided on the different, opposite surfaces of the printed circuit board. The through hole is provided for connection purposes.
FIG. 2 shows the relationship between a semiconductor chip 10, a printed circuit board 100, through holes 5, solder bumps 15, and a mother board 200. The semiconductor chip 10 is connected through connection terminals 11 to the mounting surface 32 of the printed circuit board 100. One skilled in the art would recognize that the connection terminals can be part of a package (not shown) to which the chip has been previously mounted. The printed circuit 100 is connected through the solder bumps 15 to the mother board 200. The SLC layer of FIG. 1 corresponds to the surface layer portion 13 of the printed circuit board 100 (FIG. 4). The through hole 5 is usually provided at the inner side thereof with a conductive metal layer 25 serving as a conductive channel. It is preferable that this metal layer 25 be plated with copper, but it may be plated with solder. A wire 12 extending from the chip connection terminal 11 of the semiconductor chip 10 is connected through the SLC layer 13 to the metal layer 25 and through a SLC layer 14 formed in a back surface 34 of the substrate 1 to the solder bumps 15 connected to the mother board 200.
The diameter of the through hole 5 is 0.2 mm at the lowest from the point of the drilling cost and yield. In addition, an electrode called a land 7 needs to be arranged on the opposite ends of the through hole 5, so the total diameter becomes about 0.3 mm. The relative area of the through hole 5 to the printed circuit board 100 is by no means small, and since the through hole 5 passes through the substrate 1 of the printed circuit board 100, it considerably hinders the degree of freedom of the wiring within the printed circuit board 100, including the SLC structure 13 and 14. The wiring is high in density particularly around the semiconductor chip 10, so it is not practical to provide the through holes 5 in the vicinity of the semiconductor chip 10 which hinders the degree of freedom of the wiring. Thus, the through hole 5 is indispensable for connecting the wiring layer of the chip mounting surface 32 and the wiring of the back surface 34, but, on the other hand, it hinders increasing the density of the wiring. Therefore, the through holes 5 have so far been arranged in the opposite outer end portions 36 of the printed circuit board 100, as shown in FIG. 2.
However, in this structure, the wiring leading from the chip connection terminal 11 to the solder bump 15 becomes longer and causes noise and delay. Forming the through hole 5 in the vicinity of the chip 10 is the easiest way for solving the problems, but since the density of the wiring is very high in the vicinity of the chip 10, it is not possible to form the through hole 5 in the vicinity of the chip 10, which considerably affects the wiring density. Therefore, in view of the wiring density, the position where a through hole 5 is formed will become a position away from the chip 10 by some distance. Thus, the through hole 5 and the chip 10 need to be spaced by a certain distance l, so a high integration is hindered. In other words, the wiring length from the chip connection terminal 11 to the solder bump 15 has to be not less than at least 2l.
Substrates where through holes are filled up with insulation resin and conductive paste have been developed in recent years. For example, PUPA 4-287906 discloses a substrate in which through holes are filled up with conductive material so that the elements mounted on the substrate surface and the back surface can be connected electrically. However, this invention is for mounting thin-film elements, and adopts such a substrate where elements can be mounted on the back surface, in order to avoid the disadvantage (magnetic influence, etc.) as thin-film elements are mounted on the same surface. The invention disclosed in the above publication does not have the object of the present invention that the wiring length between the chip and solder ball is shortened and the degree of freedom of the wiring is improved, thereby achieving high integration.
Japan Laid-Open Patent Publication No. HEI 6-164149 discloses a method of fabricating a multilayer printed substrate having through holes filled up with conductive paste. Japan Laid-Open Patent Publication No. HEI 2-142198 discloses a method in which unit wiring plates formed with through holes are stacked so that the through holes are vertically aligned with each other, and after they are bonded together, a conductive layer is formed in a through opening constituted by a plurality of through holes. However, in these publications there is no description for the connection between a chip to be mounted and a board, and the methods disclosed therein cannot achieve the object of the present invention.
PUPA 6-45506 filed by the assignee of the present application discloses a method of electrically connecting the both surfaces of a substrate, without using through holes, by only a via-hole. However, the present invention has a different object because the present invention relates to improve the conventional combination of through holes and SLC structure. PUPA 6-45506 connects both surfaces by forming the via holes only with building up without using the substrate. It is impossible, however, to assure the strength for the entire structure only with the via holes and without using the substrate. Since a semiconductor package is distributed as a product, it is necessary to have a certain degree of strength in view of its handling. A substrate provides necessary strength. Then, when packaging is performed by using a substrate with high strength such as a glass-epoxy substrate or a metal substrate, electrical connection between both surfaces cannot be attained by the via hole, and through holes must be used. The via hole is formed by a process such as etching. However, it is very difficult to form a through hole by completely etching the substrate. Therefore, PAPU 6-45506 is based on a presumption totally different from the present invention.
Another drawback of using the through hole lies in that the wiring of the SLC layer is prevented by the presence of the through hole because the through hole completely passes through the substrate. For example, as shown at a position 20 in FIG. 2, if a through hole exists, the wiring in the SLC layer is completely broken. The through hole 5 cannot be positioned near the chip 10 because wiring from the connection terminals 11 is very complicated so that there is no space for a through hole 5 which would prevent the wiring and consume area near the chip 10.
It is the easiest approach that the through hole is used to form a conductive channel from one surface to the other. Therefore, the through hole cannot be completely eliminated. Accordingly, it is desired to have a structure which does not prevent the degree of freedom in providing wiring in the SLC layer while maintaining the function assuring a conductive channel from one surface to the other.